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<title>SQRTPS—Square Root of Single-Precision Floating-Point Values </title></head>
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<h1>SQRTPS—Square Root of Single-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F 51 /r</p>
<p>SQRTPS xmm1, xmm2/m128</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE</td>
<td>Computes Square Roots of the packed single-precision floating-point values in xmm2/m128 and stores the result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.128.0F.WIG 51 /r</p>
<p>VSQRTPS xmm1, xmm2/m128</p></td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Computes Square Roots of the packed single-precision floating-point values in xmm2/m128 and stores the result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.256.0F.WIG 51/r</p>
<p>VSQRTPS ymm1, ymm2/m256</p></td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Computes Square Roots of the packed single-precision floating-point values in ymm2/m256 and stores the result in ymm1.</td></tr>
<tr>
<td>
<p>EVEX.128.0F.W0 51 /r</p>
<p>VSQRTPS xmm1 {k1}{z}, xmm2/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Computes Square Roots of the packed single-precision floating-point values in xmm2/m128/m32bcst and stores the result in xmm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.0F.W0 51 /r</p>
<p>VSQRTPS ymm1 {k1}{z}, ymm2/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Computes Square Roots of the packed single-precision floating-point values in ymm2/m256/m32bcst and stores the result in ymm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.0F.W0 51/r</p>
<p>VSQRTPS zmm1 {k1}{z}, zmm2/m512/m32bcst{er}</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Computes Square Roots of the packed single-precision floating-point values in zmm2/m512/m32bcst and stores the result in zmm1 subject to writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Performs a SIMD computation of the square roots of the four, eight or sixteen packed single-precision floating-point values in the source operand (second operand) stores the packed single-precision floating-point results in the destination operand.</p>
<p>EVEX.512 encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.</p>
<p>VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are zeroed.</p>
<p>VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-tion operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.</p>
<p>128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-tion is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.</p>
<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
<p><strong>Operation</strong></p>
<p><strong>VSQRTPS (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>IF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask* THEN</p>
<p>IF (EVEX.b = 1) AND (SRC *is memory*)</p>
<p>THEN DEST[i+31:i] (cid:197) SQRT(SRC[31:0])</p>
<p>ELSE DEST[i+31:i] (cid:197) SQRT(SRC[i+31:i])</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VSQRTPS (VEX.256 encoded version)</strong></p>
<p>DEST[31:0] (cid:197)SQRT(SRC[31:0])</p>
<p>DEST[63:32] (cid:197)SQRT(SRC[63:32])</p>
<p>DEST[95:64] (cid:197)SQRT(SRC[95:64])</p>
<p>DEST[127:96] (cid:197)SQRT(SRC[127:96])</p>
<p>DEST[159:128] (cid:197)SQRT(SRC[159:128])</p>
<p>DEST[191:160] (cid:197)SQRT(SRC[191:160])</p>
<p>DEST[223:192] (cid:197)SQRT(SRC[223:192])</p>
<p>DEST[255:224] (cid:197)SQRT(SRC[255:224])</p>
<p><strong>VSQRTPS (VEX.128 encoded version)</strong></p>
<p>DEST[31:0] (cid:197)SQRT(SRC[31:0])</p>
<p>DEST[63:32] (cid:197)SQRT(SRC[63:32])</p>
<p>DEST[95:64] (cid:197)SQRT(SRC[95:64])</p>
<p>DEST[127:96] (cid:197)SQRT(SRC[127:96])</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p><strong>SQRTPS (128-bit Legacy SSE version)</strong></p>
<p>DEST[31:0] (cid:197)SQRT(SRC[31:0])</p>
<p>DEST[63:32] (cid:197)SQRT(SRC[63:32])</p>
<p>DEST[95:64] (cid:197)SQRT(SRC[95:64])</p>
<p>DEST[127:96] (cid:197)SQRT(SRC[127:96])</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VSQRTPS __m512 _mm512_sqrt_round_ps(__m512 a, int r);</p>
<p>VSQRTPS __m512 _mm512_mask_sqrt_round_ps(__m512 s, __mmask16 k, __m512 a, int r);</p>
<p>VSQRTPS __m512 _mm512_maskz_sqrt_round_ps( __mmask16 k, __m512 a, int r);</p>
<p>VSQRTPS __m256 _mm256_sqrt_ps (__m256 a);</p>
<p>VSQRTPS __m256 _mm256_mask_sqrt_ps(__m256 s, __mmask8 k, __m256 a, int r);</p>
<p>VSQRTPS __m256 _mm256_maskz_sqrt_ps( __mmask8 k, __m256 a, int r);</p>
<p>SQRTPS __m128 _mm_sqrt_ps (__m128 a);</p>
<p>VSQRTPS __m128 _mm_mask_sqrt_ps(__m128 s, __mmask8 k, __m128 a, int r);</p>
<p>VSQRTPS __m128 _mm_maskz_sqrt_ps( __mmask8 k, __m128 a, int r);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Invalid, Precision, Denormal</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type 2; additionally</p>
<table>
<tr>
<td>#UD</td>
<td>
<p>If VEX.vvvv != 1111B.</p>
<p>EVEX-encoded instruction, see Exceptions Type E2.</p></td></tr>
<tr>
<td>#UD</td>
<td>If EVEX.vvvv != 1111B.</td></tr></table></body></html>